Instruction 16-015. Assume that individual stages of the datapath have the following latencies:
IF : 250 ps
ID : 350 ps
EX : 150 ps
MEM : 300 ps
WB : 200 ps
Also, assume that instructions executed by the processor are broken down as follows: alu, beq, Iw and sw. What is the clock cycle time in a pipelined and non-pipelined processor?